1. Field of the Invention
The present invention relates to a semiconductor memory such as a multi-port memory.
2. Description of the Background Art
Recently, there have been increasing demands for a multi-port memory which is accessible by a plurality of controllers. Various circuit arrangements have, accordingly, been proposed to achieve the multi-port memory.
FIG. 9 is a block diagram showing the general arrangement of a conventional multi-port memory. Memory cells MC are arranged in matrix form as shown in FIG. 9. Although not shown, the memory cells MC in each row are connected to a write word line and a read word line, and those in each column are connected to a write bit line, a write enable line and a read bit line.
A plurality of memory cell blocks MCB (MCB0 to MCBN) are provided each including 4.times.8 memory cells MC. The memory cell blocks MCB are provided with writing circuits WC (WC0 to WCN) and reading circuits RC (RC0 to RCN), respectively.
Each of the writing circuits WC sets a bit line potential WBL to be applied to the write bit line and a write enable potential CWE to be applied to the write enable line in the respective columns of the memory cell block MCB, on the basis of a write control signal WEC and a write address WAD which are provided through a write buffer WB and input data DI (DI0 to DIN).
Each of the reading circuits RC selects a read bit line on the basis of a read control signal REC and a read address RAD which are provided through a read buffer RB, and then outputs output data DO (DO0 to DON) on the basis of a read bit line potential RBL given from the selected read bit line.
A write decoder (word line driver) DW selectively activates a write word line on the basis of the write control signal WEC and write address WAD provided through the write buffer WB.
A read decoder (word line driver) DR selectively activates a read word line on the basis of the read control signal REC and read address RAD provided through the read buffer RB.
FIG. 10 is a circuit diagram showing one memory cell MC in the memory cell blocks MCB of FIG. 9 and its associated portions. As shown in FIG. 10, inverters 1 and 2 are cross-connected to each other at their input and output to form the memory cell MC, which stores data given from a node N1 serving as the input of the inverter 1 and outputs the stored data from a node N2 serving as the output of the inverter 1. Reference numeral 3 designates a write bit line to which the write bit line potential WBL is applied; 4 designates a write word line for selecting a row of the memory cells MC in write operation; 5 designates a write NMOS transistor selected by the write word line 4 for transmitting the write bit line potential WBL from the write bit line 3; 6 designates a write enable line for selecting a column of the memory cells MC in write operation; 7 designates an NMOS transistor selected by the write enable line 6 for transmitting the write data to the node N1 of the memory cell MC; 8 designates an inverter for amplifying the data of the memory cell MC to read out the amplified data; 9 designates a read word line for selecting a row of the memory cells MC in read operation; 10 designates a read NMOS transistor selected by the read word line 9 for transmitting the read data from the node N2 of the memory cell MC; and 11 designates a read bit line for transmitting the read data to an output circuit.
The provision of the write bit line 3, the write word line 4, the write enable line 6, the read word line 9, and the read bit line 11 in isolated relation enables the write and read operations to be controlled independently. This provides a 2-port RAM including a write only port and a read only port.
FIG. 11 is a circuit diagram showing the internal arrangement of the writing circuit WC of FIG. 9. The writing circuit WC includes inverters G101 to G110, 3-input NAND gates G111 to G114 and inverters G115 to G118, as shown in FIG. 11. The write control signal WEC is applied to the inverter G101, which in turn outputs the inverted signal to first inputs of the NAND gates G111 to G114. A (write) address A0 is applied to the inverter G102, which in turn outputs the inverted signal to second inputs of the NAND gates G111 and G113. The (write) address A0 is also applied to second inputs of the NAND gates G112 and G114 through the inverters G102 and G103. A (write) address A1 is applied to the inverter G104, which in turn outputs the inverted signal to third inputs of the NAND gates G111 and G112. The (write) address A1 is also applied to third inputs of the NAND gates G113 an G114 through the inverters G104 and G105.
The output of the NAND gate G111 is applied to the inverter G115 which in turn outputs the write enable potential CWE0. The output of the NAND gate G112 is applied to the inverter G116 which in turn outputs the write enable potential CWE1. The output of the NAND gate G113 is applied to the inverter G117 which in turn outputs the write enable potential CWE2. The output of the NAND gate G114 is applied to the inverter G118 which in turn outputs the write enable potential CWE3. It should be noted that i in the CWEi (i=0 to 3) represents the columns of the memory cell block MCB.
The input data DI is transmitted through the inverter G106 and to the inverters G107, G108, G109, G110 which in turn output the write bit line potentials WBL0, WBL1, WBL2, WBL3, respectively. It should be noted that the character i in WBLi (i=0 to 3) represents the columns of the memory cell block MCB.
In the above-mentioned arrangement, the write bit line potential WBL is applied to the write bit line 3 from the writing circuit WC in write operation. The write word line 4 specifies the row of the memory cells MC subjected to the write operation, and the write enable line 6 specifies the column thereof. The NMOS transistors 5 and 7 turn on only for the specified memory cell, which is then written with data. The inverter 2 is designed to have an extremely low output current so as not to prevent the write operation, and the inverters 1 and 2 form a ratio latch.
In read operation, the read word line 9 specifies the row of the memory cells MC, and the NMOS transistor 10 turns on. The data in the memory cell MC is outputted to the read bit line 11. The reading circuit RC selects one of the plurality of read bit lines 11 to output the data of the selected read bit line in read operation in the like manner as the plurality of write enable lines 6 in write operation.
For the NMOS transistors, a gate-source voltage controls a drain-source current, and no current flows between the drain and source when the gate-source voltage is not more than a threshold voltage of the transistors. Normal NMOS transistors are constructed such that the drain and source are symmetrical, the source being of a lower voltage. The threshold voltage of the transistors varies with a potential difference between the source and a well (a region in which the drain and source are formed).
When NMOS transistors are used for inverters or logic gates, the source and well of the NMOS transistors are set to the GND potential, so that the threshold voltage is about 0.7 V. In NMOS transistors used for transfer gates such as transistors 5 and 7, the source potential is sometimes higher than the well potential, resulting in an increasing threshold voltage up to a maximum of about 1.5 V due to back gate effects.
In write operation, the writing circuit WC applies the write bit line potential WBL to the write bit line 3, and "H" (VDD) is applied to the gate of the transistors 5 and 7.
When the write bit line potential WBL is "L" (0 V), the write bit line 3 side of the transistors 5 and 7 serves as the source thereof, and the gate-source voltage of the transistors 5 and 7 is approximately equal to VDD. Thus a sufficient current flows between the drain and source, and the potential at the node N1 serving as the input of the inverter 1 is readily decreased to about 0 V.
On the other hand, when the write bit line potential WBL is "H" (VDD), the input voltage of the inverter 1 is increased through the transistors 5 and 7, and the inverter 1 side of the transistors 5 and 7 serves as the source thereof. The input voltage of the inverter 1 increases up to only the gate voltage of the transistors 5 and 7 minus the threshold voltage thereof. Further, the threshold voltage of the transistor increases due to a back gate voltage applied thereto as the source potential increases.
For correct "H" write operation, the potential at the node N1 serving as the input of the inverter 1 should be more than the threshold voltage of the inverter 1. The threshold voltage of the inverter 1, which may vary in the range of about 1/3VDD to 2/3VDD in accordance with the drive capability ratio of the two transistors forming the inverter 1, is set to about 1/3VDD for case of write operation because the "H" write operation is difficult in the circuit of FIG. 10. It has been confirmed by circuit simulation that, because the speed decreases abruptly as the memory approaches the operation limit, a voltage of 1/2VDD or more is required to be applied to the input of the inverter 1 for "H" write operation at practical speeds, and a voltage of 1/6VDD or less is sufficient for "L" write operation.
1n "L" write operation, the input voltage of the inverter 1 is enabled to decrease to about 0.3 V without difficulty, there being no problem of write operation in the VDD range of 2 to 5 V.
In "H" write operation, however, the input voltage of the inverter 1 varies with the back gate voltage as described above. Assuming that the power supply voltage VDD is 3 V or less, the input voltage of the inverter 1 decreases to about (VDD-1.2) V. When VDD&lt;2.4 V, the input voltage of the inverter 1 is not more than 1/2VDD, so that the normal write operation is difficult.
In application to a practical chip, the VDD of up to about 2.8 V allows the "H" write operation at sufficient speeds because of influences of power supply voltage drop in the chip, wafer process variation and characteristic changes with temperatures. For the forgoing masons, this memory cell construction, though applicable to VDD=3.3 V.+-.0.3 V, is difficult to be applied to VDD=3.0 V .+-.0.3 V. It is not suitable for use with low power supply voltages in consideration for the use of batteries and the further decrease of voltage in the future.
The conventional semiconductor memories such as multi-port memories as above constructed is disadvantageous in that difficulty comes in the write operation when the power supply voltage is low.
Next, we will look into the power consumption of the RAM. In general, the power consumption of a RAM is determined by the current for charging and discharging the parasitic capacitance of the bit and word lines and the current carried by a sense amplifier. The latter current may be set in accordance with the required operating speeds, and the former current is determined by the product of the parasitic capacitance and the number of potential changes for the line.
In the memory cell arrangement of the conventional semiconductor memories such as multi-port memories, potentials at the write word lines, write bit lines and write enable lines vary once for every one or two write cycles, and potentials at the read word lines and read bit lines vary once for every one or two read cycles.
Potentials vary at only the write word lines and read word lines corresponding to the row to be accessed and at only the write enable lines corresponding to the column to be accessed. It is, however, general that potentials vary at the write bit lines and read bit lines corresponding to all columns.
In particular, the write bit lines are of greater amplitude than the read bit lines. This is because the "H" level of the read bit lines is decreased from VDD by the threshold voltage of the NMOS transistor 10. In addition, potentials at the write bit lines vary in response to data input changes when no write operation occurs, resulting in maximum power consumption.
A circuit arrangement is possible in which potentials vary at only the write bit lines in the column which is required to be written. This is, however, not practical because of the complexity of the circuit and the possibility of increased delay in write operation resulting from the potential variation at the write bit lines being later than that at the write enable lines.